Fabrication Process Development for Very Large-Scale Superconductor Integrated Circuits: Progress, Challenges, and Limitations

Dec. 1 11:00-11:25

*Sergey K Tolpygo1
Lincoln Laboratory, Massachusetts Institute of Technology1

Superconductor electronics provides tremendous advantages in information processing speed and energy dissipation in comparison to semiconductor electronics, offering clock rates in excess of 100 GHz, energy dissipation below 10−19 J per bit, and essentially dissipationless data transfer. The main factor impeding wide-spread implementation of superconductor electronics, both classical and quantum, is a relatively low scale of integration. Presently, the device count and the device number density in SICs reach, respectively, about 106 active devices (Josephson junction) per circuit and about 107 devices per cm2. This integration scale is about 3 to 4 orders of magnitude lower than in the most advanced, 3-nm and 5-nm, CMOS technology nodes, resulting in a much lower functionality of superconductor integrated circuits (SICs) compared to CMOS circuits.

In order to clarify the physical and technological factors limiting the scale of integration, I will briefly review the main types of superconducting logics: a) Single Flux Quantum (SFQ) logics encoding information by magnetic flux quanta and utilizing ultrafast switching of Josephson junctions, and b) parametric logics (nSQUID, AQFP) utilizing quasi-adiabatic changes in the flux state of logic cells. Despite some differences, all superconducting logics share the same scaling relations, whereas each of them has its unique poorly scalable components.

I will review the most advanced fabrication processes developed for superconductor electronics at MIT Lincoln Laboratory and the process development being done in order to increase integration scale of superconductor electronics by a factor of 10x to 100x in the near future. In particular, replacement of essentially geometrical Nb inductors in logic cells by compact NbN or/and NbTiN kinetic inductors; transition from the current fabrication node using 248-nm deep-UV photolithogrpahy with 250 nm minimum linewidth to the 150-nm node using 193-nm photolithography; replacement of presently used externally shunted Nb/Al-AlOx/Nb Josephson junctions with critical current densities, Jc, of 100 µA/µm2 and 200 µA/µm2 by self-shunted junctions with Jc = 600 µA/µm2; and increasing the number of superconducting layers from nine to ten. I will also briefly discuss and present recent results of our efforts to develop damascene processing of superconductor ICs, using plasma enhanced chemical vapor deposition of superconducting films over narrow trenches and contact holes (vias) with subsequent planarization by metal chemical mechanical polishing.

Keywords: superconductor integrated circuit, Josephson junction, AQFP, SFQ