Next-Generation Cryogenic/Superconducting Computer Architectures

Dec. 1 11:50-12:15

*Jangwoo Kim1
Seoul National University1

On facing the end of multi-core performance and DVFS scaling, computer architects now suffer from critical challenges to further improve the performance and power efficiency with conventional room-temperature computing. To overcome the challenge, architects are now aiming to exploit cryogenic/superconducting computing in which they operate computer devices at extremely low temperatures to maximize their operation frequency with their static power consumption minimized. However, to realize the new computers by developing low-temperature optimized computers and applying them to the real field, architects are in dire need of the low-temperature device modeling and architecture simulation methodologies and should show the successful architecture and system examples.

In this work, I will first introduce the potential of cryogenic/superconducting computing from the perspective of a computer architect. Next, I will explain our modeling methodology which can accurately measure the performance and power consumption of cryogenic/superconducting computer devices and architectures. Finally, I will cover various architecture examples designed to take advantage of the target low temperatures. Among the varoius cryogenic/superconduncting architecture examples, I will focus on our recent work to develop a fault-tolerant large-scale quantum control processor built with low-temperature devices.

Keywords: Cyrogenic computing, Superconducting computing, Computer architecture, Architecture modeling